General Description

XC6VLX130T-2FFG1156I  Virtex®-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardwarecomponents to enable designers to focus on innovation as soon as their development cycle begins. 

Using the third-generation ASMBL™(Advanced Silicon Modular Block) column-based architecture, the Virtex-6 family contains multiple distinct sub-families. 

This overviewcovers the devices in the LXT, SXT, and HXT sub-families. Each sub-family contains a different ratio of features to most efficiently addressthe needs of a wide variety of advanced logic designs. 

In addition to the high-performance logic fabric, Virtex-6 FPGAs contain many builtin system-level blocks. 

These features allow logic designers to build the highest levels of performance and functionality into their FPGAbased systems. Built on a 40 nm state-of-the-art copper process technology, 

Virtex-6 FPGAs are a programmable alternative to customASIC technology. Virtex-6 FPGAs offer the best solution for addressing the needs of high-performance logic designers, 

high-performanceDSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, connectivity, and softmicroprocessor capabilities.

Summary of Virtex-6 FPGA Features

• Three sub-families:• Virtex-6 LXT FPGAs: High-performance logic withadvanced serial connectivity

• Virtex-6 SXT FPGAs: Highest signal processingcapability with advanced serial connectivity

• Virtex-6 HXT FPGAs: Highest bandwidth serialconnectivity• Compatibility across sub-families

• LXT and SXT devices are footprint compatible inthe same package• Advanced, high-performance FPGA Logic

• Real 6-input look-up table (LUT) technology• Dual LUT5 (5-input LUT) option

• LUT/dual flip-flop pair for applications requiring richregister mix• Improved routing efficiency

• 64-bit (or two 32-bit) distributed LUT RAM optionper 6-input LUT

• SRL32/dual SRL16 with registered outputs option• Powerful mixed-mode clock managers (MMCM)

• MMCM blocks provide zero-delay buffering,frequency synthesis, clock-phase shifting, inputjitter filtering,

 and phase-matched clock division• 36-Kb block RAM/FIFOs• Dual-port RAM blocks

• Programmable- Dual-port widths up to 36 bits- Simple dual-port widths up to 72 bits

• Enhanced programmable FIFO logic• Built-in optional error-correction circuitry

• Optionally use each block as two independent18 Kb blocks• High-performance parallel SelectIO™ technology

• 1.2 to 2.5V I/O operation• Source-synchronous interfacing usingChipSync™ technology• Digitally controlled impedance (DCI) activetermination

• Flexible fine-grained I/O banking• High-speed memory interface support withintegrated write-leveling capability

• Advanced DSP48E1 slices• 25 x 18, two's complement multiplier/accumulator• Optional pipelining

• New optional pre-adder to assist filteringapplications• Optional bitwise logic functionality

• Dedicated cascade connections• Flexible configuration options• SPI and Parallel Flash interface

• Multi-bitstream support with dedicated fallbackreconfiguration logic• Automatic bus width detection

• System Monitor capability on all devices• On-chip/off-chip thermal and supply voltagemonitoring

• JTAG access to all monitored quantities• Integrated interface blocks for PCI Express® designs

• Compliant to the PCI Express Base Specification2.0• Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s) support withGTX transceivers

• Endpoint and Root Port capable• x1, x2, x4, or x8 lane support per block• GTX transceivers: up to 6.6 Gb/s

• Data rates below 480 Mb/s supported byoversampling in FPGA logic.• GTH transceivers: 2.488 Gb/s to beyond 11 Gb/s

• Integrated 10/100/1000 Mb/s Ethernet MAC block• Supports 1000BASE-X PCS/PMA and SGMIIusing GTX transceivers

• Supports MII, GMII, and RGMII using SelectIOtechnology resources• 2500Mb/s support available

• 40 nm copper CMOS process technology• 1.0V core voltage (-1, -2, -3 speed grades only)

• Lower-power 0.9V core voltage option (-1L speedgrade only)

• High signal-integrity flip-chip packaging available instandard or Pb-free package options

Virtex-6 FPGA Feature Summary T

able 1: Virtex-6 FPGA Feature Summary by Device Device Logic Cells Configurable Logic Blocks (CLBs) 

XC6VLX75T 74,496 11,640 1,045 288 312 156 5,616 6 1 4 12 0 9 360 

XC6VLX130T 128,000 20,000 1,740 480 528 264 9,504 10 2 4 20 0 15 600 

XC6VLX195T 199,680 31,200 3,040 640 688 344 12,384 10 2 4 20 0 15 600 

XC6VLX240T 241,152 37,680 3,650 768 832 416 14,976 12 2 4 24 0 18 720 

XC6VLX365T 364,032 56,880 4,130 576 832 416 14,976 12 2 4 24 0 18 720

 XC6VLX550T 549,888 85,920 6,200 864 1,264 632 22,752 18 2 4 36 0 30 1200 

XC6VLX760 758,784 118,560 8,280 864 1,440 720 25,920 18 0 0 0 0 30 1200

 XC6VSX315T 314,880 49,200 5,090 1,344 1,408 704 25,344 12 2 4 24 0 18 720 

XC6VSX475T 476,160 74,400 7,640 2,016 2,128 1,064 38,304 18 2 4 36 0 21 840

 XC6VHX250T 251,904 39,360 3,040 576 1,008 504 18,144 12 4 4 48 0 8 320 

XC6VHX255T 253,440 39,600 3,050 576 1,032 516 18,576 12 2 2 24 24 12 480 X

C6VHX380T 382,464 59,760 4,570 864 1,536 768 27,648 18 4 4 48 24 18 720 

XC6VHX565T 566,784 88,560 6,370 864 1,824 912 32,832 18 4 4 48 24 18 720 

Notes: 1. Each Virtex-6 FPGA slice contains four LUTs and eight flip-flops, only some slices can use their LUTs as distributed RAM or SRLs. 

2. Each DSP48E1 slice contains a 25 x 18 multiplier, an adder, and an accumulator. 

3. Block RAMs are fundamentally 36 Kbits in size. Each block can also be used as two independent 18 Kb blocks. 

4. Each CMT contains two mixed-mode clock managers (MMCM). 

5. Refer to UG517, Virtex-6 FPGA Integrated Block for PCI Express User Guide for supported core pinouts by package. 

6. This table lists individual Ethernet MACs per device. 

7. Does not include configuration Bank 0. 8. This number does not include GTX or GTH transceivers.

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